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e 6/16/97 3:50 pm 24232304.doc intel confidential (until publication date) june 1997 order number 242323-004 n compatible with large software base - ms-dos*, windows*, os/2*, unix* n 32-bit cpu with 64-bit data bus n superscalar architecture - two pipelined integer units are capable of 2 instructions/clock - pipelined floating point unit n separate code and data caches - 8k code, 8k writeback data - mesi cache protocol n advanced design features - branch prediction - virtual mode extensions n 3.3v bicmos silicon technology n 4m pages for increased tlb hit rate n ieee 1149.1 boundary scan n internal error detection features n sl enhanced power management features - system management mode - clock control n fractional bus operation - 75-mhz core / 50-mhz bus the pentium ? processor is fully compatible with the entire installed base of applications for dos*, windows*, os/2*, and unix*, and all other software that runs on any earlier intel 8086 family product. the pentium processor's superscalar architecture can execute two instructions per clock cycle. branch prediction and separate caches also increase performance. the pipelined floating-point unit delivers workstation level performance. separate code and data caches reduce cache conflicts while remaining software transparent. the pentium processor (610\75) has 3.3 million transistors, is built on intel's advanced 3.3v bicmos silicon technology, and has full sl enhanced power management features, including system management mode (smm) and clock control. the additional sl enhanced features, 3.3v operation, and the tcp package, which are not available in the pentium processor (510\60, 567\66), make the pentium processor (610\75) tcp ideal for enabling mobile pentium processor designs. the pentium processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available upon request. pentium? processor at icomp? index 610\75 mhz
pentium ? processor (610\75) e 6/16/97 3:50 pm 24232304.doc intel confidential (until publication date) contents page 1.0. introduction................................................2 1.1. pentium ? processor (610\75) spga specifications and differences from the tcp package.............................................................2 2.0. microprocessor architecture overview ...........................................................3 2.1. pentium ? processor family architecture........4 3.0. tcp pinout......................................................7 3.1. tcp pinout and pin descriptions...................7 3.1.1. pentium ? processor (610\75) tcp pinout .........................................................7 3.1.2. pin cross reference table for pentium ? processor (610\75) tcp................8 3.2. design notes................................................10 3.3. quick pin reference.....................................10 3.4. pin reference tables...................................19 3.5. pin grouping according to function.............22 4.0. pentium ? processor (610\75) tcp electrical specifications......................23 4.1. maximum ratings.........................................23 4.2. dc specifications.........................................23 page 4.3. ac specifications..........................................25 4.3.1. power and ground.......................25 4.3.2. decoupling recommendations25 4.3.3. connection specifications ......26 4.3.4. ac timings for a 50-mhz bus.......26 4.4. i/o buffer models..........................................35 4.4.1. buffer model parameters........38 4.4.2. signal quality specifications .39 4.4.2.1. ringback.........................................40 4.4.2.2. settling time...................................40 5.0. pentium ? processor (610\75) tcp mechanical specifications.....................42 5.1. tcp package mechanical diagrams............42 6.0. pentium ? processor (610\75) tcp thermal specifications...............................................47 6.1. measuring thermal values...........................47 6.2. thermal equations........................................47 6.3. tcp thermal characteristics........................47 6.4. pc board enhancements ..............................47 6.4.1. standard test board configuration ......................................48 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merc hantab ility, or infri ngement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation 1996, 1997. * third-party brands and names are the property of their respective owners.
pentium ? processor (610\75) 1 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 1. 0. introduction intel is now manufacturing its latest version of the pentium ? processor family that is designed specifically for mobile systems, with a core frequency of 75 mhz and a bus frequency of 50 mhz. the pentium processor (610\75) is provided in the tcp (tape carrier package) and spga packages, and has all of the advanced features of the pentium processor (735\90, 815\100) . the new pentium processor (610\75) tcp package has several features which allow high- performance notebooks to be designed with the pentium processor, including the following: tcp package dimensions are ideal for small form-factor designs. the tcp package has superior thermal resistance characteristics. 3.3v v cc reduces power consumption by half (in both the tcp and spga packages). the sl enhanced feature set, which was initially implemented in the intel486? cpu. the architecture and internal features of the pentium processor (610\75) tcp and spga packages are identical to those of the pentium processor (735\90, 815\100) , although several features have been eliminated for the pentium processor (610\75) tcp, as described in section 1.1. this document should be used in conjunction with the pentium processor documents listed below. list of related documents: pentium ? processor family developer?s manual, vol. 1 (order number: 241428) pentium ? processor family developer?s manual, vol. 3: architecture and programming manual (order number: 241430) 1.1. pentium ? processor (610\75) spga specifications and differences from the tcp package this section provides references to the pentium processor (610\75) spga specifications and describes the major differences between the pentium processor (610\75) spga and tcp packages. all pentium processor (610\75) spga specifications, with the exception of power consumption, are identical to the pentium processor (735\90, 815\100) specifications provided in the pentium ? processor family developer?s manual, volume 1 . see tables 8 and 11 in section 4.2 for the pentium processor (610\75) spga and tcp power specifications. the following features have been eliminated for the pentium processor (610\75) tcp: the upgrade feature, the dual processing (dp) feature, and the master/checker functional redundancy feature. table 1 lists the corresponding pins which exist on the pentium processor (610\75) spga but have been removed on the pentium processor (610\75) tcp.
pentium ? processor (610\75) 2 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 1 . spga signals removed in tcp signal function adsc# additional address status. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. brdyc# additional burst ready. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. cputyp cpu type. this signal is used for dual processing systems. d/p# dual/primary processor identification. this signal is only used for an upgrade processor. frcmc# functional redundancy checking. this signal is only used for error detection via processor redundancy, and requires two pentium processors (master/checker). pbgnt# private bus grant. this signal is only used for dual processing systems. pbreq# private bus request. this signal is used only for dual processing systems. phit# private hit. this signal is only used for dual processing systems. phitm# private modified hit. this signal is only used for dual processing systems. the i/o buffer models provided in section 4.4 of this document apply to both the pentium processor (610\75) tcp and spga packages, although the capacitance (c p ) and inductance (l p ) parameter values differ between the two packages. also, the thermal parameters, t case max and q ca , differ between the tcp and spga packages. for pentium processor (610\75) spga values, refer to chapters 24 and 26 of the pentium ? processor family developer?s manual, volume 1 . 2. 0. microprocessor architecture overview the pentium processor at icomp ? rating 610\75 mhz extends the intel pentium family of microprocessors. it is compatible with the 8086/88, 80286, intel386? dx cpu, intel386 sx cpu, intel486? dx cpu, intel486 sx cpu, intel486 dx2 cpus, the pentium processor at icomp index 510\60 mhz and icomp index 567\66 mhz, and the pentium processor at icomp index 735\90 mhz and icomp index 815\100 mhz. the pentium processor family consists of the new pentium processor at icomp rating 610\75 mhz, described in this document, the original pentium processor (510\60, 567\66), and the pentium processor (735\90, 815\100) . the name " pentium processor (610\75) " will be used in this document to refer to the pentium processor at icomp rating 610\75 mhz. "pentium processor" will be used in this document to refer to the entire pentium processor family in general. the pentium processor family architecture contains all of the features of the intel486 cpu family, and provides significant en hancements and additions including the following: superscalar architecture dynamic branch prediction pipelined floating-point unit improved instruction execution time separate 8k code and 8k data caches writeback mesi protocol in the data cache 64-bit data bus bus cycle pipelining address parity internal parity checking execution tracing performance monitoring ieee 1149.1 boundary scan system management mode
pentium ? processor (610\75) 3 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) virtual mode extensions 2.1. pentium ? processor family architecture the application instruction set of the pentium processor family includes the complete intel486 cpu family instruc tion set with extensions to accommodate some of the additional functionality of the pentium processors. all application software written for the intel386 and intel486 family microprocessors will run on the pentium processors without modification. the on-chip memory management unit (mmu) is completely compatible with the intel386 family and intel486 family of cpus. the pentium processors implement several enhancements to increase performance. the two instruc tion pipelines and floating-point unit on pentium processors are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in the pentium processors. to support this, pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the btb so the needed code is almost always prefetched before it is needed for execution. the floating-point unit has been completely redesigned over the intel486 cpu. faster algorithms provide up to 10x speed-up for common operations including add, multiply, and load. pentium processors include separate code and data caches integrated on-chip to meet per form- ance goals. each cache is 8 kbytes in size, with a 32-byte line size and is 2-way set as sociative. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the mesi protocol. the data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are also triple ported to support snooping and split line accesses. individual pages can be configured as cacheable or non-cacheable by software or hardware. the caches can be enabled or disabled by software or hardware. the pentium processors have increased the data bus to 64 bits to improve the data transfer rate. burst read and burst writeback cycles are supported by the pentium processors. in addition, bus cycle pipe lining has been adde d to allow two bus cycles to be in progress simultaneously. the pentium processors' memory management unit contains optional extensions to the architecture which allow 2-mbyte and 4-mbyte page sizes. the pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking, and in ternal parity checking features have been added along with a new exception, the ma chine check exception. as more and more functions are integrated on chip, the complexity of board level test ing is increased. to address this, the pentium processors have increased test and debug capability. the pentium processors implement ieee boundary scan (standard 1149.1). in addition, the pentium processors have specified 4 breakpoint pins that correspond to each of the de bug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to in crease performance by reducing the number of times it is necessary to trap to a vir tual 8086 monitor.
pentium ? processor (610\75) 4 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 1 . pentium ? processor block diagram
pentium ? processor (610\75) 5 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) the block diagram shows the two instruction pipelines, the "u" pipe and the "v" pipe. the u-pipe can execute all integer and floating point instructions. the v-pipe can exe cute simple integer instructions and the fxch floating-point instructions. the separate caches are shown, the code cache and data cache. the data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the pentium processor. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. the decode unit decodes the prefetched instructions so the pentium processor can execute the instruction. the control rom contains the microcode which controls the sequence of operations that must be performed to implement the pentium processor architecture. the control rom unit has direct control over both pipelines. the pentium processors contain a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. the architectural features introduced in this section are more fully described in the pentium ? processor family developer?s manual .
pentium ? processor (610\75) 6 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 3. 0. tcp pinout 3.1. tcp pinout and pin desc riptions 3.1.1. pentium ? processor (610\75) tcp pinout figure 2 . pentium ? processor (610\75) tcp pinout
pentium ? processor (610\75) 7 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 3.1.2. pin cross reference table for pentium ? processor (610\75) tcp table 2 . tcp pin cross reference by pin name address a3 219 a9 234 a15 251 a21 200 a27 208 a4 222 a10 237 a16 254 a22 201 a28 211 a5 223 a11 238 a17 255 a23 202 a29 212 a6 227 a12 242 a18 259 a24 205 a30 213 a7 228 a13 245 a19 262 a25 206 a31 214 a8 231 a14 248 a20 265 a26 207 data d0 152 d13 132 d26 107 d39 87 d52 62 d1 151 d14 131 d27 106 d40 83 d53 61 d2 150 d15 128 d28 105 d41 82 d54 56 d3 149 d16 126 d29 102 d42 81 d55 55 d4 146 d17 125 d30 101 d43 78 d56 53 d5 145 d18 122 d31 100 d44 77 d57 48 d6 144 d19 121 d32 96 d45 76 d58 47 d7 143 d20 120 d33 95 d46 75 d59 46 d8 139 d21 119 d34 94 d47 72 d60 45 d9 138 d22 116 d35 93 d48 70 d61 40 d10 137 d23 115 d36 90 d49 69 d62 39 d11 134 d24 113 d37 89 d50 64 d63 38 d12 133 d25 108 d38 88 d51 63
pentium ? processor (610\75) 8 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 2 . tcp pin cross reference by pin name (contd.) control a20m# 286 breq 312 hitm# 293 pm1/bp1 29 ads# 296 buschk# 288 hlda 311 prdy 318 ahold 14 cache# 21 hold 4 pwt 299 ap 308 d/c# 298 ierr# 34 r/s# 198 apchk# 315 dp0 140 ignne# 193 reset 270 be0# 285 dp1 127 init 192 scyc 273 be1# 284 dp2 114 intr/lint0 197 smi# 196 be2# 283 dp3 99 inv 15 smiact# 319 be3# 282 dp4 84 ken# 13 tck 161 be4# 279 dp5 71 lock# 303 tdi 163 be5# 278 dp6 54 m/io# 22 tdo 162 be6# 277 dp7 37 na# 8 tms 164 be7# 276 eads# 297 nmi/lint1 199 trst# 167 boff# 9 ewbe# 16 pcd 300 w/r# 289 bp2 28 ferr# 31 pchk# 316 wb/wt# 5 bp3 25 flush# 287 pen# 191 brdy# 10 hit# 292 pm0/bp0 30 apic clock control picclk 155 picd1 158 bf 186 stpclk# 181 picd0 156 [apicen] clk 272 [dpen#]
pentium ? processor (610\75) 9 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 2 . tcp pin cross reference by pin name (contd.) v cc 1* 2 6* 11* 17* 19 23 27* 33* 35 41* 43 49* 51 57* 59 65* 67 73 79 85 91 97 103 109 111* 117 123 129 135 141 147 153* 157* 160 165* 168* 170* 172* 174* 177* 178 180* 183* 188* 190* 195* 204 210 216 217* 221 225* 226 230 232* 236 240* 241 243* 247 249* 253 257* 258 260* 264 266* 268* 275 281 291 295 301 304* 306 309* 313 317* v ss 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 173 176 179 182 187 189 194 203 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320 nc 175 184 185 271 note: *these v cc pins are 3.3v supplies for the pentium processor (610\75) tcp but will be lower voltage pins on future offerings of this microprocessor family. all other v cc pins will remain at 3.3v. 3.2. design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc . unused active high inputs should be connected to gnd (v ss ). no connect (nc) pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. 3.3. quick pin reference this section gives a brief functional description of each of the pins. for a detailed description, see the "hardware interface" chapter in the pentium ? processor family developer?s manual , vol ume 1 .
pentium ? processor (610\75) 10 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) note that all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. table 3 . quick pin reference symbol type name and function a20m# i when the address bit 20 mask pin is asserted, the pentium processor (610\75) emulates the address wraparound at 1 mbyte which occurs on the 8086. when a20m# is asserted, the pentium processor (610\75) masks physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a31-a3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31-a5. ads# o the address status indicates that a new valid bus cycle is currently being driven by the pentium processor (610\75) . ahold i in response to the assertion of address hold , the pentium processor (610\75) will stop driving the address lines (a31-a3), and ap in the next clock. the rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the pentium processor (610\75) with even parity information on all pentium processor (610\75) generated cycles in the same clock that the address is driven. even parity must be driven back to the pentium processor (610\75) during inquire cycles on this pin in the same clock as eads# to ensure that correct parity check status is indicated by the pentium processor (610\75) . apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the pentium processor (610\75) has detected a parity error on the address bus during inquire cycles. apchk# will remain active for one clock each time a parity error is detected. [apicen] picd1 i the advanced programmable interrupt controller enable pin enables or disables the on-chip apic interrupt controller. if sampled high at the falling edge of reset, the apic is enabled. apicen shares a pin with the programmable interrupt controller data 1 signal . be7#-be5# be4#-be0# o i/o the byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the cpu for the current cycle. the byte enables are driven in the same clock as the address lines (a31 -3). t he lower four byte enables (be3#-be0#) are used on the pentium processor (610\75) as apic id inputs and are sampled at reset.
pentium ? processor (610\75) 11 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function [ bf ] i bus frequency determines the bus - to - core frequency ratio. bf is sampled at reset, and cannot be changed until another non-warm ( 1 ms) assertion of reset. additionally, bf must not change values while reset is active. for proper operation of the pentium processor (610\75) this pin should be strapped high or low. when bf is strapped to v cc , the processor will operate at a 2/3 bus/core frequency ratio. when bf is strapped to v ss , the processor will operate at a 1/2 bus/core frequency ratio. if bf is left floating, the pentium processor (610\75) defaults to a 2/3 bus ratio. note the pentium processor (610\75) will not operate at a 1/2 bus/core frequency ratio. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the pentium processor (610\75) will float all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the pentium processor (610\75) restarts the aborted bus cycle(s) in their entirety. bp[3:2] pm/bp[1:0] o the breakpoint pins (bp3-0) correspond to the debug registers, dr3-dr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the pentium processor (610\75) data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. breq o the bus request output indicates to the external system that the pentium processor (610\75) has internally generated a bus request. this signal is always driven whether or not the pentium processor (610\75) is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, the pentium processor (610\75) will latch the address and control signals in the machine check registers. if, in addition, the mce bit in cr4 is set, the pentium processor (610\75) will vector to the machine check exception. cache# o for pentium processor (610\75) -initiated cycles the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). if this pin is driven inactive during a read cycle, the pentium processor (610\75) will not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle).
pentium ? processor (610\75) 12 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function clk i the clock input provides the fundamental timing for the pentium processor (610\75) . its frequency is the operating frequency of the pentium processor (610\75) external bus and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst#, and picd0-1 are specified with respect to the rising edge of clk. d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. d63-d0 i/o these are the 64 data lines for the processor. lines d7-d0 define the least significant byte of the data bus; lines d63-d56 define the most significant byte of the data bus. when the cpu is driving the data lines, they are driven during the t2, t12, or t2p clocks for that cycle. during reads, the cpu samples the data bus when brdy# is returned. dp7-dp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the pentium processor (610\75) with even parity information on writes in the same clock as write data. even parity information must be driven back to the pentium processor (610\75) on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the pentium processor (610\75) . dp7 applies to d63-d56; dp0 applies to d7-d0. [dpen#] picd0 i/o d ual processing enable is an output of the dual processor and an input of the p rimary p rocessor. the dual processor drives dpen# low to the primary processor at r eset to indicate that the primary processor should enable dual processor mode. since the dual processing feature is not supported on the pentium processor (610\75) tcp package, dpen# should never be asserted (low) at reset. dpen# shares a pin with picd0. eads# i this signal indicates that a valid external address has been driven onto the pentium processor (610\75) address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the pentium processor (610\75) generates a write, and ewbe# is sampled inactive, the pentium processor (610\75) will hold off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating point error pin is driven active when an unmasked floating point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using dos-type floating point error reporting.
pentium ? processor (610\75) 13 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function flush# i when asserted, the cache flush input forces the pentium processor (610\75) to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle will be generated by the pentium processor (610\75) indicating completion of the writeback and invalidation. if flush# is sampled low when reset transitions from high to low, tristate test mode is entered. hit# o the hit indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either the pentium processor (610\75) data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the pentium processor (610\75) cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the pentium processor (610\75) has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda will be driven inactive and the pentium processor (610\75) will resume driving the bus. if the pentium processor (610\75) has a bus cycle pending, it will be driven in the same clock that hlda is de-asserted. hold i in response to the bus hold request , the pentium processor (610\75) will float most of its output and input/output pins and assert hlda after completing all outstanding bus cycles. the pentium processor (610\75) will maintain its bus in this state until hold is de-asserted. hold is not recognized during lock cycles. the pentium processor (610\75) will recognize hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. if a parity error occurs on a read from an internal array, the pentium processor (610\75) will assert the ierr# pin for one clock and then shutdown. ignne# i this is the ignore numeric error input. this pin has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0, and the ignne# pin is asserted, the pentium processor (610\75) will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the pentium processor (610\75) will execute the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the pentium processor (610\75) will stop execution and wait for an external interrupt.
pentium ? processor (610\75) 14 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function init i the pentium processor (610\75) initialization input pin forces the pentium processor (610\75) to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating point registers retain the values they had prior to init. init may not be used in lieu of reset after power up. if init is sampled high when reset transitions from high to low, the pentium processor (610\75) will perform built-in self test prior to the start of program execution. intr / lint0 i an active maskable interrupt input indicates that an external interrupt has been generated. if the if bit in the eflags register is set, the pentium processor (610\75) will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. if the local apic is enabled, this pin becomes local interrupt 0 . inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the pentium processor (610\75) generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle will be transformed into a burst line fill cycle. lint0/intr i if the apic is enabled, this pin is local interrupt 0 . if the apic is disabled, this pin is interrupt . lint1/nmi i if the apic is enabled, this pin is local interrupt 1 . if the apic is disabled, this pin is non-maskable interrupt . lock# o the bus lock pin indicates that the current bus cycle is locked. the pentium processor (610\75) will not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles.
pentium ? processor (610\75) 15 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the pentium processor (610\75) will issue ads# for a pending cycle two clocks after na# is asserted. the pentium processor (610\75) supports up to 2 outstanding bus cycles. nmi/lint1 i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. if the local apic is enabled, this pin becomes local interrupt 1 . pcd o the page cache disable pin reflects the state of the pcd bit in cr3, the page directory entry, or the page table entry. the purpose of pcd is to provide an external cacheability indication on a page-by-page basis. pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. if this pin is sampled active in the clock a data parity error is detected, the pentium processor (610\75) will latch the address and control signals of the cycle with the parity error in the machine check registers. if, in addition, the machine check enable bit in cr4 is set to "1", the pentium processor (610\75) will vector to the machine check exception before the beginning of the next instruction. picclk i the apic interrupt controller serial data bus clock is driven into the p rogrammable i nterrupt c ontroller c lock input of the pentium processor (610\75) . picd0-1 [dpen#] [apicen] i/o programmable i nterrupt c ontroller data lines 0-1 of the pentium processor (610\75) comprise the data portion of the apic 3-wire bus. they are open- drain outputs that require external pull-up resistors. these signals share pins with dpen# and apicen. pm/bp[1:0] o these pins function as part of the performance monitoring feature. the breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0 pins. the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active, or probe mode being entered. pwt o the page writethrough pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external writeback indication on a page-by-page basis.
pentium ? processor (610\75) 16 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function r/s# i the run / stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. a high to low transition on the r/s# pin will interrupt the processor and cause it to stop execution at the next instruction boundary. reset i reset forces the pentium processor (610\75) to begin execution at a known state. all the pentium processor (610\75) internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush# and init are sampled when reset transitions from high to low to determine if tristate test mode will be entered, or if bist will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles which are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the pentium processor (610\75) thereby causing the core to consume less power. when the cpu recognizes stpclk#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. when stpclk# is asserted, the pentium processor (610\75) will still res p ond to external snoop requests. tck i the testability clock input provides the clocking function for the pentium processor (610\75) boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the pentium processor (610\75) during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the pentium processor (610\75) on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the pentium processor (610\75) on the tdo pin on tck's falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized.
pentium ? processor (610\75) 17 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 3 . quick pin reference (contd.) symbol type name and function v cc i the pentium processor (610\75) has 79 3.3v power inputs. v ss i the pentium processor (610\75) has 72 ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. 3.4. pin reference tables table 4 . output pins name active level when floated ads# low bus hold, boff# apchk# low be7#-be5# low bus hold, boff# breq high cache# low bus hold, boff# ferr# low hit# low hitm# low hlda high ierr# low lock# low bus hold, boff# m/io#, d/c#, w/r# n/a bus hold, boff# pchk# low bp3-2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir note: all output and input/output pins are floated during tristate test mode (except tdo).
pentium ? processor (610\75) 18 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 5 . input pins name active level synchronous/ asynchronous internal resistor qualified a20m# low asynchronous ahold high synchronous bf high synchronous/reset pullup boff# low synchronous brdy# low synchronous bus state t2, t12, t2p buschk# low synchronous pullup brdy# clk n/a eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous hold high synchronous ignne# low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous pen# low synchronous brdy# picclk high asynchronous pullup r/s# n/a asynchronous pullup reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup wb/wt# n/a synchronous first brdy#/na#
pentium ? processor (610\75) 19 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 6 . input/output pins name active level when floated qualified (when an input) internal resistor a31-a3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be4#-be0# low bus hold, boff# reset pulldown* d63-d0 n/a bus hold, boff# brdy# dp7-dp0 n/a bus hold, boff# brdy# picd0[dpen#] pullup picd1[apicen] pulldown notes: all output and input/output pins are floated during tristate test mode (except tdo). *be3#-be0# have pulldowns during reset only.
pentium ? processor (610\75) 20 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 3.5. pin grouping according to function table 7 organizes the pins with respect to their function. table 7 . pin functional grouping function pins clock clk initialization reset, init address bus a31-a3, be7# - be0# address mask a20m# data bus d63-d0 address parity ap, apchk# apic support picclk, picd0-1 data parity dp7-dp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, brdy#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda interrupts intr, nmi floating point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3-2 clock control stpclk# probe mode r/s#, prdy
pentium ? processor (610\75) 21 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 4. 0. pentium ? processor (610\75) tcp electrical specifications 4.1. maximum ratings the following values are stress ratings only. functional operation at the maximum ratings is not implied or guaranteed. functional operating conditions are given in the ac and dc specification tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the pentium processor (610\75) contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. case temperature under bias ......... - 65 c to 110 c storage temperature ....................... - 65 c to 150 c 3v supply voltage with respect to v ss ........................... - 0.5v to +4.6v 3v only buffer dc input voltage .... - 0.5v to v cc + 0.5; not to exceed 4.6v (2) 5v safe buffer dc input voltage ......................... - 0.5v to 6.5v (1,3) notes: 1. applies to clk and picclk. 2. applies to all pentium processor (610\75) inputs except clk and picclk. 3. see table 9 . warning stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. 4.2. dc specifications tables 8 , 9 , and 10 list the dc specifications which apply to the pentium processor (610\75) . the pentium processor (610\75) is a 3.3v part internally. the clk and picclk inputs may be a 3.3v or 5v inputs. since the 3.3v (5v safe) input levels defined in table 9 are the same as the 5v ttl levels, the clk and picclk inputs are compatible with existing 5v clock drivers. the power dissipation specification in table 11 is provided for design of thermal solutions during operation in a sustained maximum level. this is the worst-case power the device would dissipate in a system for a sustained period of time. this number is used for design of a thermal solution for the device. table 8 . 3.3v dc specifications t case = 0 to 95 c; v cc = 3.3v 5% symbol parameter min max unit notes v il3 input low voltage - 0.3 0.8 v ttl level (3) v ih3 input high voltage 2.0 v cc +0.3 v ttl level (3) v ol3 output low voltage 0.4 v ttl level (1) (3) v oh3 output high voltage 2.4 v ttl level (2) (3) i cc3 power supply current 2650 ma @75 mhz (4) notes: 1. parameter measured at 4 ma. 2. parameter measured at 3 ma. 3. 3.3v ttl levels apply to all signals except clk and picclk. 4. this value should be used for power supply design. it was determined using a worst-case instruction mix and v cc + 5%. power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. for more information, refer to section 4.3.2.
pentium ? processor (610\75) 22 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 9 . 3.3v (5v safe) dc specifications symbol parameter min max unit notes v il 5 input low voltage - 0.3 0.8 v ttl level (1) v ih 5 input high voltage 2.0 5.55 v ttl level (1) n otes: 1 . applies to clk and picclk only. table 10 . input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf (4) c o output capacitance 20 pf (4) c i/o i/o capacitance 25 pf (4) c clk clk input capacitance 15 pf (4) c tin test input capacitance 15 pf (4) c tout test output capacitance 20 pf (4) c tck test clock capacitance 15 pf (4) i li input leakage current 15 m a 0 < v in < v cc3 (1) i lo output leakage current 15 m a 0 < v in < v cc3 (1) i ih input leakage current 200 m a v in = 2.4v (3) i il input leakage current - 400 m a v in = 0.4v (2) notes: 1. this parameter is for input without pull up or pull down. 2. this parameter is for input with pull up. 3. this parameter is for input with pull down. 4. guaranteed by design.
pentium ? processor (610\75) 23 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 11 . power dissipation requirements for thermal solution design parameter typical (1) max (2) unit notes active power dissipation 3-4 8.0 watts @ 75 mhz stop grant and auto halt powerdown power dissipation 1.2 watts @ 75 mhz (3) stop clock power dissipation .02 .05 watts (4) (5) notes: 1. this is the typical power dissipation in a system. this value was the average value measured in a system using a typical device at v cc = 3.3v running typical applications. this value is highly dependent upon the specific system configuration. 2. systems mu st be designed to thermally dissipate the maximum active power dissipation. it is determined using a worst- case instruction mix with v cc = 3.3v. the use of nominal v cc in this measurement takes into account the thermal time constant of the package. 3. stop grant/auto halt powerdown power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. 4. stop clock power dissipation is determined by asserting the stpclk# pin and then removing the external clk input. 5. complete characterization of the specification was still in process at the time of print. please contact intel for the latest information. the final specification may be less than 50 mw. 4.3. ac specifications the ac specifications of the pentium processor (610\75) consist of setup times, hold times, and valid delays at 0 pf. warning do not exceed the pentium processor (610\75) internal maximum frequency of 75 mhz by either selecting the 1/2 bus fraction or providing a clock greater than 50 mhz. 4.3.1. power and ground for clean on-chip power distribution, the pentium processor (610\75) has 79 v cc (power) and 72 v ss (ground) inputs. power and ground connections must be made to all external v cc and v ss pins of the pentium processor (610\75) . on the circuit board all v cc pins must be connected to a 3.3v v cc plane. all v ss pins must be connected to a v ss plane. 4.3.2. decoupling recommendations liberal decoupling capacitance should be placed near the pentium processor (610\75) . the pentium processor (610\75) driving its large address and data buses at high frequencies can cause transient power surges, particularly when driving large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by shortening circuit board traces between the pentium processor (610\75) and decoupling capacitors as much as possible. these capacitors should be evenly distributed around each component on the 3.3v plane. capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. for the pentium processor (610\75) , the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. a typical example would be entering or exiting the stop grant state. another example would be executing a halt instruction, causing the pentium processor (610\75) to enter the auto halt powerdown state, or transitioning from halt to the normal state. all of these examples may cause abrupt changes in the power being consumed by the pentium processor (610\75) . note that the auto halt powerdown feature is always enabled even when other power management features are not implemented. bulk storage capacitors with a low esr (effective series resistance) in the 10 to 100 f range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. in order to reduce the esr, it may be necessary to place several bulk storage capacitors in parallel.
pentium ? processor (610\75) 24 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) these capacitors should be placed near the pentium processor (610\75) (on the 3.3v plane) to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. 4.3.3. connection specifications all nc pins must remain unconnected. for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc . unused active high inputs should be connected to ground. 4.3.4. ac timings for a 50-mhz bus the ac specifications given in table 12 consist of output delays, input setup requirements and input hold requirements for a 50-mhz external bus. all ac specifications (with the exception of those for the tap signals and apic signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5v for both "0" and "1" logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct pentium processor (610\75) operation. table 12 . pentium ? processor (610\75) tcp ac specifications for 50-mhz bus operation v cc = 3.3v 5%, t case = 0 c to 95 c, c l = 0 pf symbol parameter min max unit figure notes frequency 25.0 50.0 mhz max core freq. = 75 mhz @ 2/3 t 1a clk period 20.0 40.0 ns 3 t 1b clk period stability 250 ps (1), (19) t 2 clk high time 4.0 ns 3 @2v, (1) t 3 clk low time 4.0 ns 3 @0.8v, (1) t 4 clk fall time 0.15 1.5 ns 3 (2.0v-0.8v), (1), (5) t 5 clk rise time 0.15 1.5 ns 3 (0.8v-2.0v), (1), (5) t 6a ads#, pwt, pcd, be0-7#, m/io#, d/c#, cache#, scyc, w/r# valid delay 1.0 7.0 ns 4 t 6b ap valid delay 1.0 8.5 ns 4 t 6c a3-a31, lock# valid delay 1.1 7.0 ns 4
pentium ? processor (610\75) 25 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 12 . pentium ? processor (610\75) tcp ac specifications for 50-mhz bus operation (contd.) v cc = 3.3v 5%, t case = 0 c to 95 c, c l = 0 pf symbol parameter min max unit figure notes t 7 ads#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 5 (1) t 8 apchk#, ierr#, ferr#, pchk# valid delay 1.0 8.3 ns 4 (4) t 9a breq, hlda, smiact# valid delay 1.0 8.0 ns 4 (4) t 10a hit# valid delay 1.0 8.0 ns 4 t 10b hitm# valid delay 1.1 6.0 ns 4 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 4 t 11b prdy valid delay 1.0 8.0 ns 4 t 12 d0-d63, dp0-7 write data valid delay 1.3 8.5 ns 4 t 13 d0-d63, dp0-3 write data float delay 10.0 ns 5 (1) t 14 a5-a31 setup time 6.5 ns 6 (20) t 15 a5-a31 hold time 1.0 ns 6 t 16a inv, ap setup time 5.0 ns 6 t 16b eads# setup time 6.0 ns 6 t 17 eads#, inv, ap hold time 1.0 ns 6 t 18a ken# setup time 5.0 ns 6 t 18b na#, wb/wt# setup time 4.5 ns 6 t 19 ken#, wb/wt#, na# hold time 1.0 ns 6 t 20 brdy# setup time 5.0 ns 6 t 21 brdy# hold time 1.0 ns 6 t 22 boff# setup time 5.5 ns 6 t 22a ahold setup time 6.0 ns 6 t 23 ahold, boff# hold time 1.0 ns 6
pentium ? processor (610\75) 26 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 12 . pentium ? processor (610\75) tcp ac specifications for 50-mhz bus operation (contd.) v cc = 3.3v 5%, t case = 0 c to 95 c, c l = 0 pf symbol parameter min max unit figure notes t 24 buschk#, ewbe#, hold, pen# setup time 5.0 ns 6 t 25 buschk#, ewbe#, pen# hold time 1.0 ns 6 t 25a hold hold time 1.5 ns 6 t 26 a20m#, intr, stpclk# setup time 5.0 ns 6 (11), (15) t 27 a20m#, intr, stpclk# hold time 1.0 ns 6 (12) t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 6 (11), (15), (16) t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 6 (12) t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 6 (14), (16) t 31 r/s# setup time 5.0 ns 6 (11), (15) t 32 r/s# hold time 1.0 ns 6 (12) t 33 r/s# pulse width, async. 2.0 clks 6 (14), (16) t 34 d0-d63, dp0-7 read data setup time 3.8 ns 6 t 35 d0-d63, dp0-7 read data hold time 2.0 ns 6 t 36 reset setup time 5.0 ns 7 (11), (15) t 37 reset hold time 1.0 ns 7 (12) t 38 reset pulse width, vcc & clk stable 15 clks 7 (16) t 39 reset active after vcc & clk stable 1.0 ms 7 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 7 (15), (16) t 41 reset configuration signals (init, flush#) hold time 1.0 ns 7 (12)
pentium ? processor (610\75) 27 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 12 . pentium ? processor (610\75) tcp ac specifications for 50-mhz bus operation (contd.) v cc = 3.3v 5%, t case = 0 c to 95 c, c l = 0 pf symbol parameter min max unit figure notes t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 7 to reset falling edge (15) t 42b reset configuration signals (init, flush#, brdy#, buschk#) hold time, async. 2.0 clks 7 to reset falling edge (211) t 42c reset configuration signal (brdy#, buschk#) setup time, async. 3.0 clks 7 to reset falling edge (21) t 42d reset configuration signal brdy# hold time, reset driven synchronously 1.0 ns to reset falling edge (1), (21) t 43a bf setup time 1.0 ms 7 (18) to reset falling edge t 43b bf hold time 2.0 clks 7 (18) to reset falling edge t 43c apicen setup time 2.0 clks 7 to reset falling edge t 43d apicen hold time 2.0 clks 7 to reset falling edge t 44 tck frequency ? 16.0 mhz t 45 tck period 62.5 ns 3 t 46 tck high time 25.0 ns 3 @2v, (1) t 47 tck low time 25.0 ns 3 @0.8v, (1) t 48 tck fall time 5.0 ns 3 (2.0v?0.8v), (1), (8), (9) t 49 tck rise time 5.0 ns 3 (0.8v?2.0v), (1), (8), (9) t 50 trst# pulse width 40.0 ns 9 (1), asynchronous t 51 tdi, tms setup time 5.0 ns 8 (7) t 52 tdi, tms hold time 13.0 ns 8 (7) t 53 tdo valid delay 3.0 20.0 ns 8 (8) t 54 tdo float delay 25.0 ns 8 (1), (8) t 55 all non-test outputs valid delay 3.0 20.0 ns 8 (3), (8), (10)
pentium ? processor (610\75) 28 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 12 . pentium ? processor (610\75) tcp ac specifications for 50-mhz bus operation (contd.) v cc = 3.3v 5%, t case = 0 c to 95 c, c l = 0 pf symbol parameter min max unit figure notes t 56 all non-test outputs float delay 25.0 ns 8 (1), (3), (8), (10) t 57 all non-test inputs setup time 5.0 ns 8 (3), (7), (10) t 58 all non-test inputs hold time 13.0 ns 8 (3), (7), (10) apic ac specifications t 60a picclk frequency 2.0 16.66 mhz t 60b picclk period 60.0 500.0 ns 3 t 60c picclk high time 9.0 ns 3 t 60d picclk low time 9.0 ns 3 t 60e picclk rise time 1.0 5.0 ns 3 t 60f picclk fall time 1.0 5.0 ns 3 t 60g picd0-1 setup time 3.0 ns 6 to picclk t 60h picd0-1 hold time 2.5 ns 6 to picclk t 60i picd0-1 valid delay (ltoh) 4.0 38.0 ns 4 from picclk, (22) t 60j picd0-1 valid delay (htol) 4.0 22.0 ns 4 from picclk, (22) notes: notes 2, 6, and 14 are general and apply to all standard ttl signals used with the pentium processor family. 1. not 100% tested. guaranteed by design. 2. ttl input test waveforms are assumed to be 0 to 3v transitions with 1v/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8v/ns clk input rise/fall time 8v/ns. 6. 0.3v/ns input rise/fall time 5v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation, do not use the boundary scan timings (t 55 - 58 ). 11. setup time is required to guarantee recognition on a specific clock. 12. hold ti me is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5v. 14. to guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 17. the d/c#, m/io#, w /r#, cache#, and a5-a31 signals are sampled only on the clk that ads# is active. 18. bf should be strapped to v cc or v ss .
pentium ? processor (610\75) 29 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 19. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 20. timing t 14 is required for external snooping (e.g., address setup to the clk in which eads# is sampled active). 21. buschk# is used as a reset configuration signal to select buffer size. 22. this assumes an external pullup resistor to v cc and a lumped capacitive load. the pullup resistor must be between 150 ohms and 1k ohms, the capacitance must be between 20 pf and 240 pf, and the rc product must be between 3 ns and 36 ns. ** each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays. figure 3 . clock waveform
pentium ? processor (610\75) 30 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 4 . valid delay timings figure 5 . float delay timings
pentium ? processor (610\75) 31 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 6 . setup and hold timings figure 7 . reset and configuration timings
pentium ? processor (610\75) 32 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 8 . test timings figure 9 . test reset timings
pentium ? processor (610\75) 33 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 4.4. i/o buffer models this section describes the i/o buffer models of the pentium processor (610\75) . the first order i/o buffer model is a simplified representation of the complex input and output buffers used in the pentium processor (610\75) . figures 10 and 11 show the structure of the input buffer model and figure 12 shows the output buffer model. tables 13 and 14 show the parameters used to specify these models. although simplified, these buffer models will accurately model flight time and signal quality. for these parameters, there is very little added accuracy in a complete transistor model. the following two models represent the input buffer models. the first model, figure 10 , represents all of the input buffers of the pentium processor (610\75) except for a special group of input buffers. the second model, figure 11 , represents these special buffers. these buffers are the inputs: ahold, eads#, ken#, wb/wt#, inv, na#, ewbe#, boff#, clk, and picclk. figure 10 . input buffer model, except special group
pentium ? processor (610\75) 34 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 11 . input buffer model for special group
pentium ? processor (610\75) 35 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 13 . parameters used in the specification of the first order input buffer model parameter description cin minimum and maximum value of the capacitance of the input buffer model. lp minimum and maximum value of the package inductance. cp minimum and maximum value of the package capacitance. rs diode series resistance d1, d2 ideal diodes figure 12 shows the structure of the output buffer model. this model is used for all of the output buffers of the pentium processor (610\75) . figure 12 . first order output buffer model table 14 . parameters used in the specification of the first order output buffer model parameter description dv/dt minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model. ro minimum and maximum value of the output impedance of the output buffer model. co minimum and maximum value of the capacitance of the output buffer model. lp minimum and maximum value of the package inductance. cp minimum and maximum value of the package capacitance. in addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. these diodes have been optimized to provide esd protection and provide some level of clamping. although the diodes are not required for simulation, it may be more difficult to meet specifications without them. note, however, some signal quality specifications require that the diodes be removed from the input model. the series resistors (rs) are a part of the diode model. remove these when removing the diodes from the input model.
pentium ? processor (610\75) 36 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 4.4.1. buffer model parameters this section gives the parameters for each pentium processor (610\75) input, output, and bidirectional signal, as well as the settings for the configurable buffers. some pins on the pentium processor (610\75) have selectable buffer sizes. these pins use the configurable output buffer eb2. table 15 shows the drive level for brdy# required at the falling edge of reset to select the buffer strength. the buffer sizes selected should be the appropriate size required; otherwise ac timings might not be met, or too much overshoot and ringback may occur. there are no other selection choices; all of the configurable buffers get set to the same size at the same time. table 15 . buffer selection chart environment brdy# buffer selection typical stand alone component 1 eb2 loaded component 0 eb2a notes: for correct buffer selection, the buschk# signal must be held inactive (high) at the falling edge of reset. for the pentium processor (610\75) spga version, brdyc# is used to configure selectable buffer sizes. please refer to table 16 for the groupings of the buffers. table 16 . signal to buffer type signals type driver buffer type receiver buffer type clk i er0 a20m#, ahold, bf, boff#, brdy#, buschk#, eads#, ewbe#, flush#, hold, ignne#, init, intr, inv, ken#, na#, nmi, pen#, picclk, r/s#, reset, smi#, stpclk#, tck, tdi, tms, trst#, wb/wt# i er1 apchk#, be[7:5]#, bp[3:2], breq, ferr#, ierr#, pcd, pchk#, pm0/bp0, pm1/bp1, prdy, pwt, smiact#, tdo, u/o# o ed1 a[31:21], ap, be[4:0]#, cache#, d/c#, d[63:0], dp[8:0], hlda, lock#, m/io#, scyc i/o eb1 eb1 a[20:3], ads#, hitm#, w/r# i/o eb2a eb2 hit# i/o eb3 eb3 pid0, picd1 i/o eb4 eb4 the input, output and bidirectional buffer values are listed in table 17. this table contains listings for all three types, do not get them confused during simulation. when a bidirectional pin is operating as an input, just use the cin, cp and lp values; if it is operating as a driver, use all of the data parameters.
pentium ? processor (610\75) 37 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 17 . input, output and bidirectional buffer model parameters buffer type transition dv/dt (v/nsec) ro (ohms) cp (pf) lp (nh) co/cin (pf) min max min max min max min max min max er0 rising 0.3 0.4 3.9 5.0 0.8 1.2 (input) falling 0.3 0.4 3.9 5.0 0.8 1.2 er1 rising 0.2 0.5 3.1 6.0 0.8 1.2 (input) falling 0.2 0.5 3.1 6.0 0.8 1.2 ed1 rising 3/3.0 3.7/0.9 21.6 53.1 0.3 0.6 3.7 6.6 2.0 2.6 (output) falling 3/2.8 3.7/0.8 17.5 50.7 0.3 0.6 3.7 6.6 2.0 2.6 eb1 rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.5 2.9 6.1 2.0 2.6 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.5 2.9 6.1 2.0 2.6 eb2 rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.5 3.1 6.4 9.1 9.7 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.5 3.1 6.4 9.1 9.7 eb2a rising 3/2.4 3.7/0.9 10.1 22.4 0.2 0.5 3.1 6.4 9.1 9.7 (bidir) falling 3/2.4 3.7/0.9 9.0 21.2 0.2 0.5 3.1 6.4 9.1 9.7 eb3 rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.4 3.2 4.1 3.3 3.9 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.4 3.2 4.1 3.3 3.9 eb4 rising 3/3.0 3.7/0.9 21.6 53.1 0.3 0.4 4.0 4.1 5.0 7.0 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.3 0.4 4.0 4.1 5.0 7.0 table 18 . input buffer model parameters: d (diodes) symbol parameter d1 d2 is saturation current 1.4e-14a 2.78e-16a n emission coefficient 1.19 1.00 rs series resistance 6.5 ohms 6.5 ohms tt transit time 3 ns 6 ns vj pn potential 0.983v 0.967v cj0 zero bias pn capacitance 0.281 pf 0.365 pf m pn grading coefficient 0.385 0.376 4.4.2. signal quality specifications signals driven by the system into the pentium processor (610\75) must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. there are two signal quality parameters: ringback and settling time.
pentium ? processor (610\75) 38 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 4.4.2.1. ringback excessive ringback can contribute to long-term reliability degradation of the pentium processor (610\75) , and can cause false signal detection. ringback is simulated at the input pin of a component using the input buffer model. ringback can be simulated with or without the diodes that are in the input buffer model. ringback is the absolute value of the maximum voltage at the receiving pin below v cc (or above v ss ) relative to v cc (or v ss ) level after the signal has reached its maximum voltage level. the input diodes are assumed present. maximum ringback on inputs = 0.8v (with diodes) if simulated without the input diodes, follow the maximum overshoot/undershoot specification. by meeting the overshoot/undershoot specification, the signal is guaranteed not to ringback excessively. if simulated with the diodes present in the input model, follow the maximum ringback specification. overshoot (undershoot) is the absolute value of the maximum voltage above v cc (below v ss ). the guideline assumes the absence of diodes on the input. maximum overshoot/undershoot on 5v 82497 cache controller, and 82492 cache sram inputs (clk and picclk only) = 1.6v above v cc5 (without diodes) maximum overshoot/undershoot on 3.3v pentium processor (610\75) inputs (not clk and picclk) = 1.4v above v cc3 (without diodes) figure 13 . overshoot/undershoot and ringback guidelines 4.4.2.2. settling time the settling time is defined as the time a signal requires at the receiver to settle within 10 percent of v cc or v ss . settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. on a physical board, second-order effects and other effects serve to dampen the signal at the receiver. because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. settling time
pentium ? processor (610\75) 39 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) may be simulated with the diodes included or excluded from the input buffer model. if diodes are included, settling time recommendation will be easier to meet. although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. use the following procedure to verify board simulation and tuning with concerns for settling time. 1. simulate settling time at the slow corner for a particular signal. 2. if settling time violations occur, simulate signal trace with d.c. diodes in place at the receiver pin. the d.c. diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. 3. if settling time violations still occur, simulate flight times for 5 consecutive cycles for that particular signal. 4. if flight time values are consistent over the 5 simulations, settling time should not be a concern. if however, flight times are not consistent over the 5 simulations, tuning of the layout is required. 5. note that, for signals that are allocated 2 cycles for flight time, the recommended settling time is doubled. a typical design method would include a settling time that ensures a signal is within 10% of v cc or v ss for at least 2.5 ns prior to the end of the clk period. figure 14 . settling time
pentium ? processor (610\75) 40 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 5. 0. pentium ? processor (610\75) tcp mechanical specifications today's portable computers face the challenge of meeting desktop performance in an environment that is constrained by thermal, mechanical, and electrical design considerations. these considerations have driven the development and implementation of intel?s tape carrier package (tcp). the intel tcp package has been designed to offer a high pin count, low profile, reduced footprint package with uncompromised thermal and electrical performance. intel continues to provide packaging solutions that meet our rigorous criteria for quality and performance, and this new entry into the intel package portfolio is no exception. key features of the tcp package include: surface mount technology design, lead pitch of 0.25 mm, polyimide body size of 24 mm and polyimide up for pick&place handling. tcp components are shipped with the leads flat in slide carriers, and are designed to be excised and lead formed at the customer manufacturing site. recommendations for the manufacture of this package are included in the pentium ? processor (610\75) tape carrier package user?s guide . figure 15 shows a cross-sectional view of the tcp package as mounted on the printed circuit board. figures 16 and 17 show the tcp as shipped in its slide carrier, and key dimensions of the carrier and package. figure 18 shows a blow up detail of the package in cross-section. figure 19 shows an enlarged view of the outer lead bond area of the package. tables 19 and 20 provide pentium processor (610\75) tcp package dimensions. 5.1. tcp package mechanical diagrams tab lead (ofc copper) gold bump polyimide support ring polyimide keeper bar thermally & electrically conductive adhesive (silver filled thermoplastic) note: sketches not to scale encapsulant die full x-section 1/2 x-section thermal vias pcb ground plane pcb figure 15 . cross-sectional view of the mounted tcp package
pentium ? processor (610\75) 41 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 16 . one tcp site in carrier (bottom view of die)
pentium ? processor (610\75) 42 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 17 . one tcp site in carrier (top view of die)
pentium ? processor (610\75) 43 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) figure 18 . one tcp site (cross-sectional detail) figure 19 . outer lead bond (olb) window detail
pentium ? processor (610\75) 44 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 19 . tcp key dimensions symbol description dimension symbol description dimension n leadcount 320 leads w tape width 48.18 0.12 l site length (43.94) reference only e1 outer lead pitch 0.25 nominal b outer lead width 0.10 0.01 d1,e1 package body size 24.0 0.1 a2 package height 75 mhz/90 mhz--0.615 0.030 120 mhz--0.605 0.030 dl die length 75 mhz/90 mhz--12.769 0.015 120 mhz--9.929 0.015 dw die width 75 mhz/90 mhz--11.755 0.015 120 mhz--9.152 0.015 lt lead thickness 75 mhz/90 mhz--0.035 mm 120 mhz--0.025 mm el encap length 75 mhz/90 mhz--(13.40 mm) reference only 120 mhz--(10.56 mm) reference only ew encap width 75 mhz/90 mhz--(12.39 mm) reference only 120 mhz--(9.78 mm) reference only notes: dimensions are in millimeters unless otherwise noted. dimensions in parentheses are for reference only. table 20 . mounted tcp package dimensions description dimension package height 0.75 max. terminal dimension 29.5 nom. package weight 0.5 g max. note: dimensions are in millimeters unless otherwise noted. package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
pentium ? processor (610\75) 45 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) 6. 0. pentium ? processor (610\75) tcp thermal specifications the pentium processor (610\75) is specified for proper operation when the case temperature, t case , (t c ) is within the specified range of 0 c to 95 c. 6.1. measuring thermal values to verify that the proper t c (case temperature) is maintained for the pentium processor (610\75) , it should be measured at the center of the package top surface (encapsulant). to minimize any measurement errors, the following techniques are recommended: use 36 gauge or finer diameter k, t, or j type thermocouples. intel's laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the center of the package top surface using highly thermally conductive cements. intel's laboratory testing was done by using omega bond (part number: ob-100). the thermocouple should be attached at a 90 angle as shown in figure 20 . figure 20 . technique for measuring case temperature (t c ) 6.2. thermal equations for the pentium processor (610\75) , an ambient temperature (t a ) is not specified directly. the only requirement is that the case temperature (t c ) is met. the ambient temperature can be calculated from the following equations: [ ] t t p t t p t t p t t p j c jc a j ja a c ca c a ja jc ca ja jc = + = - = - = + - = - q q q q q q q q ( ) where, t a and t c are ambient and case temperatures ( c) q ca = case-to-ambient thermal resistance ( c/w) q ja = junction-to-ambient thermal resistance ( c/w) q jc = junction-to-case thermal resistance ( c/w) p = maximum power consumption (watts) p (maximum power consumption) is specified in section 4.2. 6.3. tcp thermal characteristics the primary heat transfer path from the die of the tape carrier package (tcp) is through the back side of the die and into the pc board. there are two thermal paths traveling from the pc board to the ambient air. one is the spread of heat within the board and the dissipation of heat by the board to the ambient air. the other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. to prevent the possibility of damaging the tcp component, the thermal enhancements should be attached to the opposite side of the tcp site ? not directly mounted to the package surface. 6.4. pc board enhancements copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the pc board to the ambient air. tables 21 and 22 present thermal resistance data for copper plane thickness and via effects. it should be noted that although thicker copper planes will reduce the q ca of a system without any thermal enhancements, they have less effect on the q ca of a system with thermal enhancements. however, placing vias under the die will reduce the q ca of a system with and without thermal enhancements.
pentium ? processor (610\75) 46 1/16/97 9:25 am 24232302.doc intel confidential (until publication date) table 21 . thermal resistance vs. copper plane thickness with and without enhancements copper plane thickness* q ca (c/w) no enhancements q ca (c/w) with heat pipe 1 oz. cu 18 8 3 oz. cu 14 8 notes: *225 vias underneath the die (1 oz = 1.3 ml) table 22 . thermal resistance vs. thermal vias underneath the die no. of vias under the die* q ca (c/w) no enhancements 0 15 144 13 note: *3 oz. copper planes in test boards 6.4.1. standard test board configuration all tape carrier package (tcp) thermal measurements provided in the following tables were taken with the component soldered to a 2" x 2" test board outline. this six-layer board contains 225 vias (underneath the die) in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. for the pentium processor (610\75) tcp, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). the die is attached to the die attach pad using a thermally and electrically conductive adhesive. this test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board. note thermal resistance values should be used as guidelines only, and are highly system dependent. final system verification should always refer to the case temperature specification. table 23 . pentium ? processor (610\75) tcp package thermal resistance without enhancements q jc (c/w) q ca (c/w) thermal resistance without enhancements .8 13.9 table 24 . pentium ? processor (610\75) tcp package thermal resistance with enhancements (without airflow) thermal enhancements q ca (c/w) notes heat sink 11.7 1.2" 1.2" .35" al plate 8.7 4" 4" .030" al plate with heat pipe 7.8 .3 1" 4" table 25 . pentium ? processor (610\75) tcp package thermal resistance with enhancements (with airflow) thermal enhancements q ca (c/w) notes heat sink with fan @ 1.7 cfm 5.0 1.2" 1.2" .35" hs 1" 1" .4" fan heat sink with airflow @ 400 lfm 5.1 1.2" 1.2" .35" hs heat sink with airflow @ 600 lfm 4.3 1.2" 1.2" .35" hs hs = heat sink lfm = linear feet/minute cfm = cubic feet/minute

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